1. Field of the Invention
The present invention relates to a solid state image device, in particular to a solid state image device suitable to an image system of acquiring a moving picture or images at a high frame rate to synthesize them to form an image and a camera using it.
2. Related Background Art
FIG. 10 is a block diagram showing a prior art solid state image device. This has been disclosed, for example, in Japanese Patent Application Laid-Open No. H11-196332 being a Japanese patent. The solid state image device in FIG. 10 has a pixel 1 which converts an optical signal to an electric signal, a photoelectric converter 2 with a plurality of pixels 1 being arranged two-dimensionally, a vertical shift register 3 (VSR1) which selects the two-dimensionally arranged pixels sequentially on a row-by-row basis in the vertical direction. Moreover, the solid state image device in FIG. 10 has a line memory unit 4 that retains each pixel signal of a selected line and a horizontal shift register 5 (HSR1) that scans signals of each pixel stored in the line memory unit 4 sequentially in the horizontal direction to transfer to a read out circuit 10.
Here, the photoelectric converter 2 shows an example of 6 rows by 8 columns, but the pixel arrangement is not limited thereto and optional. In addition, the read out circuit 10 has an operational amplifier 6 of bringing signals from the line memory unit 4 into impedance conversion and a gain control amplifier (AGC) 8 of adjusting signal gains and subtracting offset levels set by a DA converter 7 from signal levels to adjust offset levels. Moreover the read out circuit 10 is configured by including an AD converter 9 of converting an output of the gain control amplifier 8 to a digital signal.
At the time of acquiring an image with a solid state image device, a method of converting, into electric signals, optical signals derived by pixels having undergone radiation with operation of a shutter during a constant storage period to output is general. As for a shutter, there is means that shields light radiated to an image device with a mechanical shutter as in a camera apparatus, but there is also a case of a solid state image device itself electrically operating shutter operations.
In particular, in the solid state image device with a CMOS (complementary field effect transistor), a general method is a slit rolling shutter operation, that is, a method of scanning a vertical shift register twice during a single image pickup period, a first scan resetting each pixel to commence storage and a second scan completing storage to output signals.
Operations of this solid state image device will be described in detail with reference to FIG. 11 and FIG. 12. FIG. 11 is a circuit diagram showing the photoelectric conversion unit 2 shown in FIG. 10, a line memory unit 4 and an operational amplifier 6, being a part of the read out circuit 10, of bringing signals from the line memory unit 4 into impedance conversion. A pixel 1 is configured by a photodiode D1 of converting an optical signal into a electrical signal, a transfer switch Q1 for transferring an electric charge stored in the photodiode D1 to a gate of a transistor Q2 that configures a source follower, a reset switch Q3 for resetting the gate of the transistor Q2 and a row selection switch Q4.
Here, the pixel arrangement will be described with an example of, but not limited to, 2 rows by 2 columns. Reference character Q5 denotes a constant current circuit to become a load of the vertical output line 11 to which the row selection switch of each pixel is connected. Reference characters CTS1 to 2 and CTN1 to 2 denote capacitors being line memories respectively. Reference characters Q6 and Q7 denote transfer switches for writing pixel outputs of a selected row to the line memories. Reference characters Q8 and Q9 denote transfer switches of reading out signals from the line memories to the horizontal output lines 12 and 13. Reference characters CHS and CHN denote load capacitors of the horizontal output lines 12 and 13. Reference characters Q10 and Q11 denote reset switches for resetting the capacitors CHS and CHN. Here, the vertical shift register 3 and the horizontal shift register 5 are omitted for simplifying the description.
FIG. 12 is a timing chart showing operations of the circuit in FIG. 11. When the vertical shift register 3 operates, for a selected 1st row, a reset pulse PRESB1, a transfer pulse PTX1 and a row selection pulse PSEL1 are outputted. At first, as described above, the first scan of the vertical shift register implements shutter line scanning, but in order to make descriptions readily understandable, the second scan of the vertical shift register, that is, read out line scanning will be described first.
In FIG. 12, read out line scanning starts at the time t14, a row selection pulse PSEL1 will move to a high level while a reset pulse PRES1B will move to a low level. Moreover, a source follower Q2 of the selected row is connected to the vertical output line 11 and a gate thereof will come into a floating state so as to become capable of accepting a signal charge from the photodiode D1.
However, at this time, since the gate of the source follower Q2 gives rise to reset noise Vn to therefore result in an S/N drop, correction is necessary. Under the circumstance, the transfer switch Q7 is turned ON with a transfer pulse PTN at the time t15 so that the reset noise Vn is transferred to the line memories CTN1 to 2. Next, during the period of the time t16 to t17, the transfer switch Q1 is turned ON by the transfer pulse PTX1, then the signal electric charge stored in the photodiode D1 is transferred to the gate of the source follower Q2 and undergoes voltage conversion with the gate capacitance of Q2.
The gate voltage at this time will be a sum Vs+Vn between a component Vs derived by a signal electric charge and a reset noise component Vn. Thereafter, at the time t18, the transfer switch Q6 is turned ON by a transfer pulse PTS so that the signal is transferred to the line memories CTS1 to 2. Next, at the time t19, PTX1 and PRESLB return to high levels, and the gates of the photodiode D1 and the source follower Q2 are short-circuited to a reset potential (here, power supply) by a reset switch Q3 are both reset. Thereafter, at the time t20, the row selection pulse PSEL1 will move to a low level so that the source follower Q2 of each pixel is cut off from the vertical output line 11 so that signal transfer from the pixel of the selected row to the line memory unit 4 is completed.
When operations so far are over, the step moves to a horizontal read out operation from the time t21. The horizontal read out operation transfers signals retained in the respective line memories CTS1 to 2 and CTN1 to 2 to the load capacitors CHS and CHN of the horizontal output lines 12 and 13 respectively. As for horizontal read out, firstly, a horizontal output line reset pulse PCHR moves to a high level to turn ON Q10 to 11 to reset CHS and CHN. Next, the shift pulse PH1 of the horizontal shift register 5 moves to a high level to turn ON the transfer switches Q8 and 9 so that the line memories CTS1 and CTN1 and the horizontal output lines 12 and 13 get electrically conductive.
Thus, the signals retained by the line memories CTS1 and CTN1 undergo capacitance division into CHS and CHN respectively and are inputted to the read out circuit 6. The read out circuit 6 buffers the respective transferred signals and thereafter implements subtraction processing. That is, an output of the read out circuit 6 is derived by
                    CTS        ⁢                                  ⁢        1        ×                              (                          Vs              +              Vn                        )                    /                      (                                          CTS                ⁢                                                                  ⁢                1                            +              CHS                        )                              -              CTN        ⁢                                  ⁢        1        ×                              (            Vn            )                    /                      (                                          CTN                ⁢                                                                  ⁢                1                            +              CHN                        )                                =          CTS      ×                        (          Vs          )                /                  (                      CTS            +            CHS                    )                    ⁢                          ⁢              (                              ∵                          CTS              ⁢                                                          ⁢              1                                =                      CTN            ⁢                                                  ⁢            1                          )              ,expressing that the above described reset noise Vn is cancelled.
Next, the horizontal output lines 12 and 13 are reset again with PHCR and signals of the next pixel are read out from CTS2 and CTN2 with the horizontal shift pulse PH2. So far, read out for one row selected by a series of vertical operations and horizontal operations is all completed. Thereafter, the vertical shift register scans to select the subsequent row at the time t22 and the above described operations are repeated.
As described above, storage of optical signals at the photoelectric converter 2 is over at the point of time (time t17) when the transfer switch Q1 turns OFF subject to transfer of a signal electrical charge to a gate of the source follower Q2, and therefore the period since the shutter is operated until transfer operation is completed will become storage hours. A slit rolling shutter operation is to implement exactly the same operations as the above described read out operations prior to read out scanning, intended to implement shutter operations electrically inside a solid state image device.
That is, in FIG. 12, a first operation of vertical shift register starts at the time t1. Difference from the above described read out line scanning is that the row selection pulse PSEL1 remains at a low level. The reason thereof is that there is no need to make an access to the line memory since the object of a shutter operation is to rest a pixel.
Thereafter, reset of a pixel and a gate of a source follower Q2 starts at the time t5 and ends at the time t6, and then the photodiode will get to a floating state so as to become capable of storing a photoelectric charge. That is, storage hours will be from the time t6 to the time t17. In addition, in order to equalize storage hours of respective rows, although each pixel and the vertical output line are not electrically conductive, also at the time of shutter operations, a line memory writing period and a dummy reading period equivalent to substantial reading for a horizontal read out operation are necessary. Pulses during these shutter periods are indicated by broken lines in FIG. 12, but these pulses are not always required to be outputted.
In the configuration of a prior art solid state image device as described above, in order to read out the output of each row as shown in FIG. 13 thoroughly, a series of operation period is required as follows:
shutter→transfer 1 (pixel→line memory)→dummy reading (line memory→horizontal output)→storage→transfer 1 (pixel→line memory)→substantial reading (line memory→horizontal output).
Accordingly, a period T1 to read out an output for 1 frame will take long and a number of frames required for a case of filming a moving picture etc. will not be derived. In addition, since the storage starting time of each row is different, an image will skew as shown in FIG. 14 to deteriorate an image quality. Or in such a system that the pictured images were patched together to form a piece of image later, there was a disadvantage that seams between images were misaligned at last, etc.